Title :
A real-time image feature vector generator employing functional cache memory for edge flags
Author :
Nakagawa, Takuki ; Shibata, Tadashi
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
A feature-vector-generation VLSI architecture has been developed aiming at building real-time image recognition systems based on the directional edge based algorithm. The functional cache memory developed in the present work cyclically buffers newly extracted edge flags from an input image, while supplying edge flags to a vector generation circuitry. As a result, it has become possible to generate a 64-dimetional feature vector in every cycle of operation. The chip was designed in a 0.18-mum 5-metal CMOS technology and sent to fabrication, and correct operation of the entire system was confirmed by Nanosim simulation. The architecture enables us to generate 3.9 times 107 feature vectors/sec (@100 MHz), which is 5 times 103 times faster than the software processing using 2.16-GHz processor.
Keywords :
CMOS integrated circuits; VLSI; cache storage; feature extraction; image recognition; CMOS technology; Nanosim simulation; VLSI architecture; directional edge based algorithm; edge flags; frequency 2.16 GHz; functional cache memory; real-time image feature vector generator; real-time image recognition systems; size 0.18 mum; software processing; vector generation circuitry; Buildings; CMOS technology; Cache memory; Circuit simulation; Computer architecture; Fabrication; Image generation; Image recognition; Real time systems; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118440
