A systolic computation scheme of time-delay neural networks

Author

Pérez-castellanos, M. ; Rodellar, V. ; Bobadilla, J. ; Peinado, V. ; Gòmez-vilda, P.

Author_Institution

Fac. de Inf., Univ. Politecnica de Madrid, Spain

fYear

1993

fDate

16-18 Aug 1993

Firstpage

1093

Abstract

The basic idea developed in this paper is to study the viability of computing a TDNN algorithm in a systolic architecture. The main problem to adopt this kind of solution resides in the presence of the digital filter part of the NN algorithm. Such an irregularity requires the inclusion of some additional external hardware for the proper treatment of the data inputs to the pipeline. The external hardware proposed consists in two similar elements named distributor and collector. The complete algorithm is computed with the restriction of having available a pipeline of only four processors due to limitations in the area of silicon. To solve this problem, some partitioning and mapping techniques have been applied. Finally a brief discussion regarding performance aspects and conclusions are presented

Keywords

VLSI; delay circuits; digital filters; neural chips; pipeline processing; systolic arrays; TDNN algorithm; VLSI; digital filter part; mapping techniques; partitioning; pipeline; systolic architecture; systolic computation scheme; time-delay neural networks; Computer architecture; Computer networks; Digital filters; Feeds; Hardware; Neural networks; Partitioning algorithms; Pipelines; Silicon; Speech processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343275

Filename

343275