Low-power multiplier optimized by Partial-Product Summation and adder cells

This work presents a low-power multiplier using a dynamic-range determination (DRD) unit and a modified upper/lower left-to-right (ULLR) structure in the partial-product summation (PPS) unit. Prior to executing a multiplication, effective dynamic ranges of two input data are estimated by the DRD unit to determine that these input data with smaller and larger dynamic ranges are multiplier and multiplicand for Booth decoding, respectively. Such approach can exhibit that partial products in high precision have a high chance of being zero. Due to this phenomenon, the ULLR structure is modified by moving the correction bits from the upper part to the lower part of the PPS unit to reduce switching power. Additionally, various 10-transistor adder cells are investigated to find out the adequate ones in upper and lower parts of the PPS unit for power conservation. By using in-house cells and standard cells of the TSMC 1P6M 0.18-mum CMOS technology, the proposed and conventional multipliers are implemented and simulated by the Power-mill and Time-mill tools. The simulated results demonstrate that the proposed multiplier consumes the least power than the conventional ones in multimedia computing.