Efficient systolic architecture and power modeling for finite ridgelet transform

In this paper, an efficient architecture for the finite ridgelet transform (FRIT) suitable for embedded computer vision systems based on a parallel, systolic finite radon transform (FRAT) sub-block and Haar wavelet transform (HWT) block is presented. Field programmable gate array (FPGA) implementation is carried out to characterise the performance of the proposed FRIT architecture. Additionally, a high level power macromodeling and analysis methodology that enables accurate characterisation of power consumption as a function of various design and performance metrics is presented. The mathematical models that are derived allow the system designer to make intelligent trade-offs when incorporating the developed cores as sub-blocks in hardware based image and video processing systems.