DocumentCode
2266317
Title
An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation
Author
Matolin, Daniel ; Schreiter, Jörg ; Getzlaff, Stefan ; Schüffny, René
Author_Institution
Dresden University of Technology, Germany
fYear
2004
fDate
7-10 Sept. 2004
Firstpage
51
Lastpage
55
Abstract
We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.
Keywords
Biological neural networks; Biomembranes; CMOS technology; Coupling circuits; Humans; Image segmentation; Neural networks; Neurons; Prototypes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on
Print_ISBN
0-7695-2080-4
Type
conf
DOI
10.1109/PCEE.2004.11
Filename
1376734
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