An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation

We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.