Title :
A Process for optimizing probe and final test through parameter matching
Author :
Shumaker, J. ; Lauderdale, M.
Author_Institution :
Motorola, Austin, TX, USA
fDate :
30 Sept.-2 Oct. 2003
Abstract :
Most manufacturing facilities use a wafer level test operation to screen die functionality before die are diced and packaged. This process is designed to save the cost of packaging non-functional die. Differences between the probe and final test environment can lead to apparent differences in die performance. This paper describes a method to manage differences between test environments and optimize the overall return of a two pass test flow. Underlying theory is presented along with practical examples and witnessed results.
Keywords :
integrated circuit packaging; die functionality; final test environment; nonfunctional die; optimizing probe; packaging; parameter matching; two pass test flow; wafer level test operation; Assembly; Costs; Optimization methods; Packaging; Performance evaluation; Probes; Process design; Production facilities; Testing; Wafer scale integration;
Conference_Titel :
Semiconductor Manufacturing, 2003 IEEE International Symposium on
Print_ISBN :
0-7803-7894-6
DOI :
10.1109/ISSM.2003.1243319