DocumentCode
2266428
Title
A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip
Author
Wu, Li-Wei ; Tang, Wei-Xiang ; Hsu, YarSun
Author_Institution
Dept. of Electr. Eng., Nat. T sing Hua Univ., Hsinchu, Taiwan
fYear
2011
fDate
26-28 May 2011
Firstpage
177
Lastpage
182
Abstract
Hybrid networks, which combine the flexibility of packet-switched network and the low-latency of circuit-switched network, provide decent performance. However, users are obligated to maintain the configuration of temporary circuit-switched connection. In this paper, we propose Dynamic Bypass Circuit, a novel architecture which reconfigures a mesh network according to the traffic trends of applications at run-time. Additionally, in order to create more obvious trends for Dynamic Bypass Circuit, we propose north-last-weave routing algorithm. It guides packets toward different directions according to the positions of their source nodes. Simulation results show that dynamic reconfigurable NoC which adopts Dynamic Bypass Circuit outperforms traditional packet-switched network. The latency improvement is 18.08% under Transpose traffic and on average 13.05% under three different traffic patterns.
Keywords
circuit switching; network routing; network-on-chip; reconfigurable architectures; switched networks; circuit switched network; dynamic bypass circuit; dynamic reconfigurable NoC; dynamic reconfigurable network-on-chip; hybrid network; mesh network; north last weave routing algorithm; packet switched network; routing algorithm; source node; temporary circuit switched connection; Heuristic algorithms; Monitoring; Routing; Sensors; Switches; Switching circuits; Topology; NoC; dynamic reconfigurable; north-last weave;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing with Applications (ISPA), 2011 IEEE 9th International Symposium on
Conference_Location
Busan
Print_ISBN
978-1-4577-0391-1
Electronic_ISBN
978-0-7695-4428-1
Type
conf
DOI
10.1109/ISPA.2011.38
Filename
5951902
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