Circuit techniques using stacked MOS transistors

The characteristics of the stacked MOS transistor is analyzed. Circuit design techniques based upon this device are proposed. One application is to use the stacked transistor to build a high dc gain, single-stage transconductance-C integrator. Simulation and analytical results have showed that the technique is especially useful for high-frequency filtering applications. A simple circuit technique used to obtain optimal bias voltages for MOS cascode transistors is presented. Instead of complicated level shifting or sizing calculations, the theory behind is simply exploiting the nature of stacked MOS transistors which, with gate-drain connections, emulate a single MOS diode to generate the desired bias