Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different types of gating configurations using only PMOS transistor (PMOS gating), only NMOS transistor (NMOS gating), and both types of transistors (dual gating) are examined and compared. The effectiveness of the proposed power gating technique to the combinational block therein with different data input rates is investigated. Based on the computer simulation results, we have found that Gt70% wasted power reduction (including both short-circuit and leakage powers) as compared to the conventional asynchronous-logic pipeline stage can be achieved with all gating configurations. In particular, dual gating achieves the best wasted power reduction of 86% for short-circuit power and 99% for leakage power @ 10 Mbps input rate.