An ultra-thin ALD TaN barrier for high-performance Cu interconnects

Author

Chung, Hum ; Chang, Mingchao ; Chu, S. ; Kumar, Narendra ; Goto, Keisuke ; Maity, N. ; Sankaranarayanan, Sriram ; Okamura, Hiroyuki ; Ohtsuka, N. ; Ogawa, Shinichi

Author_Institution

Appl. Mater. Inc., Santa Clara, CA, USA

fYear

2003

fDate

30 Sept.-2 Oct. 2003

Firstpage

454

Lastpage

456

Abstract

To meet the ITRS line resistance specifications for Cu interconnects at the 65 nm device node, the barrier thickness must be minimized. An ultra-thin amorphous ALD TaN barrier has been proposed that shows to be an effective barrier at 10Å thickness. Physical characterization of composition and barrier property has been presented along with electrical integration data. Line resistance and via resistance data shows that lower interconnect resistance can be obtained with ALD barriers. Interconnect reliability with the integration of ALD barriers along with stress migration data have also been discussed and presented.

Keywords

amorphous state; atomic layer deposition; copper; electric resistance; electrical resistivity; electromigration; integrated circuit interconnections; integrated circuit reliability; tantalum compounds; thin films; 10 Å; 65 nm; Cu; Cu interconnects; TaN; electrical integration; interconnect reliability; interconnect resistance; line resistance; stress migration; ultra-thin amorphous ALD TaN barrier; Amorphous materials; Atherosclerosis; Conductivity; Electric resistance; Electrical resistance measurement; Materials testing; Nitrogen; Performance analysis; Stress; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2003 IEEE International Symposium on

ISSN

1523-553X

Print_ISBN

0-7803-7894-6

Type

conf

DOI

10.1109/ISSM.2003.1243325

Filename

1243325