DocumentCode :
2266651
Title :
LOGIC product yield analysis by Wafer Bin Map pattern recognition supervised neural network
Author :
Chen, F.L. ; Sheng-Che Lin ; Young, K.L.
Author_Institution :
Nat. Tsing-hua Univ., Hsin-Chu, Taiwan
fYear :
2003
fDate :
30 Sept.-2 Oct. 2003
Firstpage :
501
Lastpage :
504
Abstract :
Wafer Bin Maps (WBMs) are important for yield improvement to trace root causes. The characteristic of WBMs patterns are formed by processes, so process engineers can collect clues from the patterns and correlate them with specific processes, and this can save much time and efforts in finding the root causes. However, the existing learning algorithms have the main shortage of product dependency. For this reason, this work adopted a supervised learning methodology to develop an on-line WBMs pattern recognition system that maps WBMs into 70×70 binary images to solve this issue. Furthermore, this work also proposed a learning scheme to recognize repeating failures that are usually viewed as random pattern in the existing approaches.
Keywords :
integrated circuit testing; integrated circuit yield; integrated logic circuits; neural nets; pattern recognition; LOGIC product; binary images; learning algorithms; neural network; wafer bin map pattern recognition; Circuit testing; Fabrication; Learning systems; Logic; Manufacturing processes; Neural networks; Pattern analysis; Pattern recognition; Semiconductor device manufacture; Statistical analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing, 2003 IEEE International Symposium on
ISSN :
1523-553X
Print_ISBN :
0-7803-7894-6
Type :
conf
DOI :
10.1109/ISSM.2003.1243336
Filename :
1243336
Link To Document :
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