VLSI implementation of a modular ANN chip for character recognition

Author

Rehan, Sameh E. ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

1993

fDate

16-18 Aug 1993

Firstpage

1279

Abstract

Dedicated mixed-mode VLSI chips, which provide a compact, fast, and flexible implementation of ANNs, can release the full power of these structures. In this paper, a sampled-data implementation of ANNs is presented. ANN model and circuit simulations are performed for a prototype MLP model architecture which solves two-character recognition problems. A novel modular ANN chip, which implements a two-character recognizer using a parallelogram VLSI architecture, is designed using a 1.2 μm CMOS technology. An extended architecture is proposed to solve multi-character recognition problems. This paper demonstrates the feasibility of a CMOS VLSI implementation of ANNs for character recognition using the developed modular ANN chip

Keywords

CMOS integrated circuits; VLSI; character recognition; character recognition equipment; circuit analysis computing; mixed analogue-digital integrated circuits; multilayer perceptrons; neural chips; neural net architecture; sampled data circuits; 1.2 micron; CMOS technology; MLP model architecture; VLSI implementation; character recognition; circuit simulations; mixed-mode VLSI chips; modular ANN chip; multi-character recognition problems; parallelogram VLSI architecture; sampled-data implementation; two-character recognition problems; CMOS technology; Character recognition; Circuit simulation; Clocks; MOSFETs; Resistors; Semiconductor device modeling; Strontium; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343333

Filename

343333