Simulation of circuit speed and leakage current in the presence of imperfect lithography

In semiconductor manufacturing, profit is strongly influenced by yield (cost) and speed (revenue). Shrinking the gate CD (Critical Dimension) improves chip speed but increases chip leakage current (subthreshold current), believed to reduce yield. Lithography influences both chip speeds and leakage. We have developed a tool to simulate both chip speed and leakage current in the presence of gate CD variations caused by lithography. This tool has been applied to an ISCAS ´95 benchmark circuit. Regression equations were extracted relating speed and leakage current to the minimum CD and various imperfections in lithography. In this example, it is revealed that the delay is sensitive to lens aberrations and flare in lithography, but not the optical proximity effect and Coma when the maximum total leakage current is below 1μA.