Title :
A multi-layer neural network architecture with external weight memory
Author :
Yazdi, N. ; Ahmadi, M. ; Shridhar, M.
Author_Institution :
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
Abstract :
An architecture for VLSI implementation of multi-layer neural networks is presented in this paper. It is based on direct utilization of external digital weight memory. The architecture lends itself easily to a chip-in-loop training scheme which is controlled by a digital host computer. This architecture has been applied for VLSI implementation of the classifier unit of a moment-invariant contour-shape recognition system
Keywords :
VLSI; image classification; image recognition; multilayer perceptrons; neural chips; neural net architecture; VLSI implementation; chip-in-loop training scheme; classifier unit; digital weight memory; external weight memory; moment-invariant contour-shape recognition system; multilayer neural network; neural network architecture; Adders; Computer architecture; Digital control; Memory architecture; Multi-layer neural network; Neural network hardware; Neural networks; Neurons; Robustness; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343335
