Title :
A scan design for asynchronous sequential logic circuits using SR-latches
Author :
Shieh, Ming-Der ; Wey, Chin-Long ; Fisher, P. David
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults
Keywords :
asynchronous circuits; asynchronous sequential logic; flip-flops; logic design; logic testing; sequential circuits; shift registers; ASLCs; SR-latches; asynchronous sequential logic circuits; clock synchronization; fault-free circuits; faulty circuits; hazards; races; scan design; stuck-at faults; testability; Circuit faults; Circuit testing; Clocks; Fault diagnosis; Hazards; Latches; Logic testing; Sequential analysis; Sequential circuits; Synchronization;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343339
