• DocumentCode
    2266753
  • Title

    Dynamically Reconfigurable Hardware for Object-Oriented Processing

  • Author

    Kühn, Andreas ; Huss, Sorin A.

  • Author_Institution
    Darmstadt University of Technology
  • fYear
    2004
  • fDate
    7-10 Sept. 2004
  • Firstpage
    181
  • Lastpage
    186
  • Abstract
    The focus of this paper is to establish a link of dynamic structures as found in software-based systems function descriptions to hardware implementations. Specific properties of object-oriented software methodologies and partially reconfigurable FPGAs are first analyzed. Then, both a reconfigurable processing unit and an approach how to map object classes to such execution units are elaborated. The feasibility of the proposed mapping method is demonstrated for some application examples.
  • Keywords
    Application software; Central Processing Unit; Computer languages; Coprocessors; Field programmable gate arrays; Hardware; Java; Object oriented modeling; Parallel processing; Reconfigurable logic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on
  • Print_ISBN
    0-7695-2080-4
  • Type

    conf

  • DOI
    10.1109/PCEE.2004.30
  • Filename
    1376754
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2266753