Title :
A synthesis procedure for large-scale asynchronous finite state machines
Author :
Kang, Jun-Woo ; Wey, Chin-Long ; Fisher, P. David
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
This paper presents an efficient synthesis procedure for asynchronous finite state machines (FSMs). A merged flow table is first generated from a behavioral description of a FSM. Based on the bipartite characteristics of the adjacency diagram, a race-free state assignment algorithm using bipartite graphs is applied. Several MCNC FSM benchmarks have been tested. Results show that the presented procedure can handle reasonably large asynchronous FSMs
Keywords :
asynchronous circuits; finite state machines; flip-flops; hazards and race conditions; logic design; sequential circuits; state assignment; MCNC FSM benchmarks; adjacency diagram; behavioral description; bipartite characteristics; bipartite graphs; clocked sequential logic circuits; edge-triggered J-K bistable element; large-scale asynchronous finite state machines; merged flow table; race-free state assignment algorithm; synthesis procedure; Analytical models; Automata; Benchmark testing; Bipartite graph; Circuit synthesis; Clocks; Equations; Large-scale systems; Merging; Sequential circuits;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343340
