DocumentCode
2266796
Title
The self-biased based PLL with fast lock circuit
Author
Xueming, Wei ; Ping, Li
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2010
fDate
28-30 July 2010
Firstpage
901
Lastpage
904
Abstract
This paper presents a design of a self-biased based PLL with fast lock circuit, which achieves process technology independence, fixed damping factor, fixed ratio bandwidth related operating frequency, and fast lock time. The lock time of the PLL could be adjusted by demand. The input reference frequency is 125 MHz and the PLL generates fixed output frequency of 1250 MHz.
Keywords
frequency response; mixed analogue-digital integrated circuits; phase locked loops; fast lock circuit; fast lock time; fixed damping factor; fixed ratio bandwidth related operating frequency; process technology independence; self-biased based PLL; CMOS integrated circuits; Charge pumps; Phase locked loops;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Circuits and Systems (ICCCAS), 2010 International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-8224-5
Type
conf
DOI
10.1109/ICCCAS.2010.5581850
Filename
5581850
Link To Document