A unified approach to chip, test, and assembly technologies for MCMs

The “post-fab” manufacturing technologies of test, assembly and packaging are taking a larger share of the final cost of complex ICs than ever before even though the cost of a wafer fab sits at unprecedented levels. These technologies have been allowed to remain static as long as they were minor cost adders, but now they need to receive the same attention in technology evolution as their better known wafer-fab rivals. The traditional approaches to packaging and test have been optimized independently of each other and of chip technology. This paper provides a re-examination of current practice and proposes a step-by-step plan toward a joint optimum for meeting the fab and post-fab constraints for high-performance microprocessor ICs. This optimum considers the fact that, particularly at high operating speeds, chips must be electrically exercised as part of their manufacture both to ensure rapid yield learning and to guarantee Known Good Die specifications