DocumentCode
2267600
Title
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture
Author
Tradowsky, Carsten ; Thoma, Florian ; Hübner, Michael ; Becker, Jürgen
fYear
2012
fDate
20-22 June 2012
Firstpage
279
Lastpage
282
Abstract
In today´s mobile computers, such as tablets and smart phones, power, performance and chip area are the major constraints to the development of cost efficient high tech products. One solution is the usage of application-specific instruction-set processors (ASIP), which are optimized for the execution of special tasks and thus enable a more efficient implementation. As an extension to this approach the LISPARC processor is developed. For more flexibility, the LISPARC model enables dynamic reconfiguration at run-time in order to adapt to different ASIPs. The processor model of LISPARC is described using an architecture description language called Language for Instruction-Set Architectures (LISA).
Keywords
hardware description languages; instruction sets; microprocessor chips; parallel architectures; ASIP; LISA; LISPARC model; LISPARC processor; Language for Instruction-Set Architectures; adaptive processor microarchitecture; application-specific instruction-set processor; architecture description language; chip area; dynamic reconfiguration; mobile computer; processor model; smart phone; tablet; task execution; Adaptation models; Computer architecture; Hardware; Microarchitecture; Pipelines; Software; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Embedded Systems (SIES), 2012 7th IEEE International Symposium on
Conference_Location
Karlsruhe
Print_ISBN
978-1-4673-2685-8
Electronic_ISBN
978-1-4673-2683-4
Type
conf
DOI
10.1109/SIES.2012.6356596
Filename
6356596
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