Title :
On multiple-valued logic design of neural networks
Author :
Jain, A.K. ; Bolton, R.J. ; Abd-El-Barr, M.H. ; Cheung, C.
Author_Institution :
Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada
Abstract :
Neural networks are massively parallel systems having a large number of neurodes, an electronic approximation of a human neuron, with numerous interconnections between them. Using multiple-valued signaling it is possible to reduce interconnection complexity compared to the use of binary signals. This paper concentrates on multiple-valued logic (MVL) realization of neural networks in a current mode CMOS technology. Basic circuit elements used to realize MVL neural networks are also given
Keywords :
CMOS logic circuits; current-mode logic; logic design; multivalued logic circuits; neural chips; MVL neural networks; current mode CMOS technology; interconnection complexity; multiple-valued logic design; multiple-valued signaling; neural networks; CMOS logic circuits; CMOS technology; Humans; Integrated circuit interconnections; Logic circuits; Logic design; Logic devices; Neural networks; Voltage; Weather forecasting;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343395
