• DocumentCode
    2268081
  • Title

    A fast algorithm to test planar topological routability

  • Author

    Lim, Andrew ; Sahni, Sartaj ; Thanvantri, Venkat

  • Author_Institution
    Information Technol. Inst., Singapore, Singapore
  • fYear
    1995
  • fDate
    4-7 Jan 1995
  • Firstpage
    8
  • Lastpage
    12
  • Abstract
    We develop a simple linear time algorithm to determine if a collection of two pin nets can be routed, topologically, in a plane (i.e. single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng (1983)
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; network routing; network topology; IC layout design; VLSI layout; fast algorithm; linear time algorithm; pin nets; planar topological routability testing; single layer routing; Computational Intelligence Society; Information technology; Merging; Pins; Rivers; Routing; Shape; Switches; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1995., Proceedings of the 8th International Conference on
  • Conference_Location
    New Delhi
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-6905-5
  • Type

    conf

  • DOI
    10.1109/ICVD.1995.512069
  • Filename
    512069
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2268081