DocumentCode
2268195
Title
Robust testing for stuck-at faults
Author
Chakraborty, Tapan J. ; Agrawal, Vishwani D.
Author_Institution
AT&T Bell Labs., Princeton, NJ, USA
fYear
1995
fDate
4-7 Jan 1995
Firstpage
42
Lastpage
46
Abstract
This paper proposes a generalization of robust tests with respect to assumptions about fault models and circuit models. The specific case of d-robust tests for single stuck-at faults is studied. These tests maintain their validity in the presence of macro-delay faults. A macro-delay of size n means that the delay of all combinational paths can be in the range [O,nT] where T is the clock period. We give a simple method of duplicating a test vector n times to produce a d-robust test for a stuck-at fault in a combinational circuit. We further implement a more complex algorithm to derive d-robust tests for stuck-at faults in sequential circuits
Keywords
combinational circuits; delays; fault diagnosis; logic testing; sequential circuits; circuit models; combinational circuit; d-robust tests; fault models; logic circuit testing; robust testing; sequential circuits; single stuck-at faults; Circuit faults; Circuit testing; Clocks; Combinational circuits; Delay effects; Electrical fault detection; Fault detection; Robustness; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512075
Filename
512075
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