Title :
A fast-multiplier generator for FPGAs
Author :
Kumar, Suthikshn ; Forward, Kevin ; Palaniswami, Marimuthu
Author_Institution :
Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
Abstract :
FPGA implementation of artificial neural networks calls for multipliers of various word length. In this paper, a new algorithm for generating variable word length multipliers for FPGA implementation is presented. The multipliers generated are based on a Booth Encoded optimized Wallace tree architecture. Several features of FPGA architecture are used to generate fast and efficient multipliers. These multipliers are shown to be 20% faster than existing FPGA multiplier implementations
Keywords :
field programmable gate arrays; multiplying circuits; neural chips; parallel architectures; Booth encoded optimized Wallace tree architecture; FPGA architecture; FPGAs; artificial neural networks; fast-multiplier generator; variable word length multipliers; Arithmetic; Costs; Field programmable gate arrays; Hardware; Logic devices; Neural networks; Programmable logic arrays; Programmable logic devices; Signal generators; Switches;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512077
