Advances of the counterflow pipeline microarchitecture

The counterflow pipeline concept was originated by R.F. Sproull et al. (1994) to demonstrate the concept of asynchronous circuits. This architecture provides better throughput via clocking and data locality within the pipeline. We have taken these ideas and reformulated them into a scalable architecture that has the same locality for clocking and data, but adds aggressive speculation, fewer pipeline stalls, and a much faster startup. A high level C++ simulator has been built to explain the design tradeoffs. A VHDL model of an implementation of CFPP has been designed to validate the concept