Title :
Functional clock schedule optimization
Author :
Aldanha, Alexander S. ; Shenoy, Narendra V. ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
All existing algorithms for clock schedule optimization are conservative since they use only topological analysis to estimate the delays of paths between latches. This paper proposes a novel algorithm that accounts for false paths (over several time frames) in level-sensitive sequential circuits to obtain tighter bounds on the optimum clock schedule than previously obtainable
Keywords :
circuit optimisation; clocks; delays; flip-flops; scheduling; sequential circuits; timing; clock schedule optimization; delays; false paths; latches; level-sensitive sequential circuits; time frames; Algorithm design and analysis; Clocks; Delay estimation; Flip-flops; Latches; Logic circuits; Optimal scheduling; Processor scheduling; Scheduling algorithm; Timing;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512084
