Title :
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
Author :
Yadavalli, Sitaram ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
In this paper we discuss a new automatic test scheduling system for architectures that use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along with the results obtained
Keywords :
automatic testing; combinational circuits; integrated circuit testing; logic testing; scheduling; MUSTC-testing; automatic test; control paths; data-paths; module level pre-computed test sets; multi-stage-combinational test; register-transfer level; signal types; test scheduling; Circuit faults; Circuit synthesis; Circuit testing; Digital signal processing; Hardware design languages; Multiplexing; Processor scheduling; Registers; Sequential analysis; System testing;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512087
