Retiming of synchronous circuits with variable topology

Generally, circuit design leads to a trade-off scenario between speed and various parameters like power dissipation, AT complexity, re-use of already existing cells, design time, etc. To deal with this trade-off the interaction between retiming and the selection of combinational elements from a set of cells with these different parameters is considered here. Additionally, modifications of the circuit graph concerning the interconnections, e.g. due to associativity of the underlying algorithm, lead to a parameterized topology. The algorithm presented an this paper combines all three, retiming, the selection of specific cells and the choice of an appropriate topology in one optimization step