Title :
Fully asynchronous, robust, high-throughput arithmetic structures
Author :
Patra, P. ; Fussell, D.S.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
This paper presents some novel circuit designs for bit serial adders and multipliers built out of some unusual, but well-defined circuit primitives. The circuits are fully delay-insensitive, provide good reliability and speed, and are easily verified. The structures are flexible and handle inputs of arbitrary lengths while being asymptotically optimal in speed and area. The scaleability of these circuits makes them. Very attractive for applications such as RSA cryptosystems which need very large operands and fast multiplication
Keywords :
VLSI; adders; asynchronous circuits; digital arithmetic; integrated logic circuits; multiplying circuits; RSA cryptosystems; bit serial adders; bit serial multipliers; delay-insensitive; fully asynchronous structures; high-throughput arithmetic structures; scaleability; Adders; Arithmetic; Asynchronous circuits; Clocks; Delay; Public key cryptography; Robustness; Switches; Throughput; Timing;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512093
