A single chip, pipelined, cascadable, multichannel, signal processor

The architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. This paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. The signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL´s 2μm double metal CMOS process and packaged in a 144 pin CPGA