Title :
Massively parallel device simulation using irregular grids
Author :
Sanghavi, J. ; Tomacruz, E. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Partitioning, communication scheduling, and preconditioning algorithms are developed to implement a parallel linear solver for an irregular grid drift-diffusion device simulator. The parallel program is executed on a 64 node CM-5 and is compared with PILS running on a single processor. We obtain an average CPU time speed-up of 46.1X for each CGS iteration with no preconditioning, and a speed-up of 33.6X for the solution of the matrix
Keywords :
digital simulation; electronic engineering computing; parallel algorithms; processor scheduling; semiconductor device models; 64 node CM-5; CPU time speed-up; communication scheduling; drift-diffusion device simulator; irregular grids; massively parallel device simulation; parallel linear solver; parallel program; partitioning algorithm; preconditioning algorithms; Computational modeling; Convergence; Eigenvalues and eigenfunctions; Grid computing; Laplace equations; Matrices; Partitioning algorithms; Processor scheduling; Robustness; Scheduling algorithm;
Conference_Titel :
Numerical Modeling of Processes and Devices for Integrated Circuits, 1994. NUPAD V., International Workshop on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-7803-1867-6
DOI :
10.1109/NUPAD.1994.343471
