High voltage SJ-pLDMOS with Variation Lateral Doping drift layer

This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific on-resistance for a given Breakdown Voltage (BV) can be achieved by using a high aspect ratio of the SJ pillars. Simulation results show that the SJ-pLDMOS with L_d of 35μm exhibits BV of 582V and R_on,SP of 210mΩ.cm², yielding to a power Figure Of Merit (FOM) of 1.6 MW/cm². These excellent device performances make the proposed SJ-pLDMOS a promising candidate for level shift circuit.