Title :
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology
Author :
Puvvada, Venugopal ; Potla, Suresh ; Selvam, Tamizh ; Suresh, P.R.
Author_Institution :
Texas Instrum. (India) Pvt. Ltd., Bangalore, India
Abstract :
The effect of using an n-guardring compared to p-guardring in preventing latchup due to remote transient at drain of I/O buffer n-channel transistor for 0.8 μm CMOS technology is studied. Steady state simulations performed using a 2D device simulator TMA-MEDICI, show that the n-guardring is more effective compared to the p-guardring in increasing the remote trigger level for latchup. It is found that an increase in substrate resistance increased the remote trigger current level for latchup
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; integrated circuit technology; transients; 0.8 micron; 2D device simulator; CMOS technology; I/O buffer n-channel transistor; TMA-MEDICI; latchup prevention; n-guardring; p-guardring; remote transient; steady state simulation; substrate resistance; Bipolar transistors; CMOS technology; Contact resistance; Electric resistance; Electrodes; Instruments; Reflection; Technical activities; Thyristors; Voltage;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512105
