DocumentCode
2269088
Title
KYOKO: a new approach to couple 2D process and device simulation
Author
Stecher, M. ; Engl, W.L.
Author_Institution
Inst. fur Theor. Elektrotech., Aachen Univ., Germany
fYear
1994
fDate
5-6 Jun 1994
Firstpage
85
Lastpage
88
Abstract
Coupled process and device simulation has become an important tool for reducing the cost of technology development. In this paper the 2D-process/device simulation interface KYOKO is introduced which coarsens the process simulated device structure to increase the device simulation efficiency drastically. In addition the influence of this coarsening step is evaluated for the example of an NMOS transistor
Keywords
MOSFET; digital simulation; doping profiles; semiconductor device models; semiconductor process modelling; 2D process simulation; KYOKO; NMOS transistor; coarsening step; device simulation; process simulated device structure; simulation efficiency; technology development; Approximation error; Costs; Doping profiles; Geometry; MOSFETs; Numerical models; Oxidation; Partial differential equations; Semiconductor process modeling; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Numerical Modeling of Processes and Devices for Integrated Circuits, 1994. NUPAD V., International Workshop on
Conference_Location
Honolulu, HI
Print_ISBN
0-7803-1867-6
Type
conf
DOI
10.1109/NUPAD.1994.343485
Filename
343485
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