An experimental low-power CMOS pipeline ADC using feedforward sample-and-hold amplifier

Author

Tam, Chi-tat ; Elmasry, Mohamed I.

Author_Institution

VLSI Res. Group, Waterloo Univ., Ont., Canada

Volume

1

fYear

1998

fDate

24-28 May 1998

Firstpage

257

Abstract

This paper describes an experimental CMOS 3.3 V 10-bit 1.5-bit-per-stage pipeline analog-to-digital converter (ADC) using a feedforward sample-and-hold amplifier (SHA) in a 5 V 0.8 μm BiCMOS process. Test results show that it achieves up to 8 bits of resolution. The chip consumes a power of 35 mW at a maximum conversion rate of 10 MS/s. The modified SHA offers several advantages such as relaxed gain requirement, lower power consumption and smaller area

Keywords

BiCMOS integrated circuits; CMOS digital integrated circuits; analogue-digital conversion; feedforward; integrated circuit measurement; integrated circuit testing; operational amplifiers; pipeline processing; sample and hold circuits; 0.8 micron; 10 bit; 3.3 V; 35 mW; 5 V; BiCMOS process; analog-to-digital converter; area; experimental low-power CMOS pipeline ADC; feedforward sample-and-hold amplifier; gain; maximum conversion rate; power consumption; resolution; test results; Adders; CMOS process; Circuits; Differential amplifiers; Error correction; Operational amplifiers; Pipelines; Switches; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1998. IEEE Canadian Conference on

Conference_Location

Waterloo, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-4314-X

Type

conf

DOI

10.1109/CCECE.1998.682731

Filename

682731