Low-voltage power-efficient BiDPL logic design and applications

This paper presents a new logic design, bipolar double pass-transistor logic (BiDPL), and its implementation into a full-adder. At 1.2 V and output loads of 0.1 to 0.7 pF the new logic style has up to 2.9 times better power efficiency than previously reported low-voltage BiCMOS styles and uses between 16 to 32 % less switching power. Under optimal conditions (V_dd=1.6 V), the new design has up to 18% higher power efficiency than conventional CMOS logic for loads of 0.55 to 1 pF and up to 117 % better power efficiency compared to BiCMOS styles for output loads of 0.1 to 0.68 pF. When used to implement a full adder, it is more power-efficient at very low power supply voltages (1.1 to 2 V) than a conventional CMOS adder design and the best low-voltage low-power adder reported in the literature. The proposed BiDPL adder outperforms in power efficiency both designs at 1.5 V by as much as 61 % and 535 % respectively