DocumentCode :
2269419
Title :
Partial scan design for technology mapped circuits
Author :
Balakrishnan, Arun ; Chakradhar, Srimat T.
Author_Institution :
RUTCOR, Rutgers Univ., New Brunswick, NJ, USA
fYear :
1995
fDate :
4-7 Jan 1995
Firstpage :
283
Lastpage :
287
Abstract :
For a vast majority of production VLSI designs, the synthesis pipeline is interrupted and technology mapping is performed manually. Here, designers map functional specifications directly onto a more richer set of library blocks that include counters and registers. Typically, these blocks have more than one memory element. The scan version of such a block has all flip-flops chained into a shift register during test mode. For such designs, we show that existing partial scan selection methods may produce sub-optimal solutions. We then propose a new method of selecting scan flip-flops in mapped designs. Our algorithm is based on a new formulation that models the presence of multiple memory elements in a library block and also takes into account both area and performance penalties of scan. We also extend a recently proposed integer linear program (ILP) formulation. A graph transformation that was effective in solving the scan selection problem for large synthesized (or unmapped) designs is shown to be inapplicable for mapped designs. We then develop a new transformation that provably preserves optimum solutions for these mapped designs. Experimental results on three production VLSI circuits having 12,000 to over 50,000 gates are reported
Keywords :
VLSI; circuit CAD; design for testability; flip-flops; graph theory; integer programming; integrated circuit design; integrated logic circuits; linear programming; logic CAD; logic design; VLSI design; functional specifications; integer linear program formulation; library block; multiple memory elements; partial scan design; production VLSI circuits; scan flip-flops selection; technology mapped circuits; Circuit synthesis; Circuit testing; Counting circuits; Flip-flops; Libraries; Pipelines; Production; Sequential analysis; Shift registers; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
ISSN :
1063-9667
Print_ISBN :
0-8186-6905-5
Type :
conf
DOI :
10.1109/ICVD.1995.512125
Filename :
512125
Link To Document :
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