Title :
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering
Author :
Borah, Manjit ; Irwin, Mary Jane ; Owens, Robert M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
In this paper we present new techniques to reduce the power consumption of a static CMOS circuit by enlarging transistors in high fan-out gates and reordering inputs to the gates. The techniques are developed based on observations from results of hspice simulations. These methods are incorporated into a performance and power constrained module generator, PowerSizer. Experimental results from the module generator on several real circuits show that as much as 15% saving in power consumption can be obtained on arithmetic circuits with almost no tradeoff in area or delay
Keywords :
CMOS logic circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; minimisation; PowerSizer; arithmetic circuits; high fan-out gates; input reordering; logic circuits; power constrained module generator; power consumption minimisation; static CMOS circuits; transistor sizing; CMOS logic circuits; Capacitance; Computer science; Energy consumption; Leakage current; Power dissipation; Power generation; Pulse inverters; Switching circuits; Threshold voltage;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512127