Title :
A new methodology for the design of low-cost fail safe circuits and networks
Author :
Kishore, B. Ravi ; Parekhji, R.A. ; Pagey, Sandeep ; Sherlekar, S.D. ; Venkatesh, G.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
Abstract :
Fail safe circuits find widespread application in safety critical electronic systems. This paper presents a new methodology for their design. The main contributions of the paper are formulation of the design of fail safe circuits and networks as input-output encoding problems, and proposing a new output encoding technique based on graph embedding for their low-cost design. This design methodology is independent of the functional dependence between the inputs and outputs, and provides a systematic framework for exploring different implementations of fail safe circuits for graceful degradation
Keywords :
combinational circuits; encoding; graph theory; logic partitioning; combinational circuits; design methodology; graceful degradation; graph embedding; input-output encoding problems; low-cost design; low-cost fail safe circuits; output encoding technique; safety critical electronic systems; systematic framework; Application software; Binary codes; Circuit faults; Computer science; Costs; Degradation; Design methodology; Encoding; Safety; Tin;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512138
