Title :
A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS
Author :
Nedovic, N. ; Kristensson, A. ; Parikh, S. ; Reddy, S. ; Walker, W. ; McLeod, S. ; Tzartzanis, N. ; Tamura, H. ; Kanda, K. ; Yamamoto, T. ; Matsubara, S. ; Kibune, M. ; Doi, Y. ; Ide, S. ; Tsunoda, Y. ; Yamabana, T. ; Shibasaki, T. ; Tomita, Y. ; Hamada,
Author_Institution :
Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
Abstract :
A 2 times 21.5-22.3 Gb/s to 4 times 10.7-11.2 Gb/s SF15.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 times 20 Gb/s data from a TIA and outputs SF15.2 4 times 10 Gb/s data and 10 Gb/s deskew channel. The serializer receives SF15.2 inputs and outputs 2 times 20 Gb/s for the optical DQPSK modulator. Although inductor-peaked CML is needed in the deserializer 20 Gb/s input limiting amplifier (LA) and the serializer output stages, power reduction to 3 W for both IC´s is effected by deserializing to 16 times 2.5 Gb/s internally and implementing the core logic using standard CMOS circuits.
Keywords :
CMOS integrated circuits; amplifiers; field effect MIMIC; limiters; transponders; SF15.2 compliant two-chip SerDes; TIA data; bit rate 10.7 Gbit/s to 11.2 Gbit/s; bit rate 20 Gbit/s; bit rate 22.3 Gbit/s to 21.5 Gbit/s; bit rate 40 Gbit/s; core logic; deserializer; deskew channel; inductor-peaked CML; input limiting amplifier; optical DQPSK modulator; optical transponder module; serializer output stages; size 65 nm; standard CMOS circuits; CMOS logic circuits; Laboratories; Optical amplifiers; Optical filters; Optical modulation; Optical sensors; Phase locked loops; Power amplifiers; Stimulated emission; Transponders;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium, 2009. CISC 2009. Annual IEEE
Conference_Location :
Greensboro, NC
Print_ISBN :
978-1-4244-5191-3
Electronic_ISBN :
1550-8781
DOI :
10.1109/csics.2009.5315637
