Title :
Sampling jitter correction using factor graphs
Author :
Bolliger, Lukas ; Loeliger, Hans-Andrea
Author_Institution :
Dept. of Inf. Technol. & Electr. Eng., ETH Zurich, Zurich, Switzerland
fDate :
Aug. 29 2011-Sept. 2 2011
Abstract :
Analog-to-digital converters are impaired by sampling clock jitter. The error induced by clock jitter depends on the slope of the analog signal at the sampling instant. In this paper, a continuous-time state space model allows to estimate the slope of the continuous-time signal, which is then used in an iterative algorithm for jitter correction.
Keywords :
analogue-digital conversion; clocks; graph theory; jitter; analog signal slope; analog-to-digital converters; continuous-time signal slope estimation; continuous-time state space model; factor graphs; iterative algorithm; sampling clock jitter; sampling jitter correction; Clocks; Estimation; Iterative methods; Jitter; Noise measurement; Signal to noise ratio;
Conference_Titel :
Signal Processing Conference, 2011 19th European
Conference_Location :
Barcelona
