• DocumentCode
    2270798
  • Title

    Framework for fast and accurate performance simulation of multiprocessor systems

  • Author

    Cheung, Eric ; Hsieh, Harry ; Balarin, Felice

  • Author_Institution
    Univ. of California Riverside, Riverside
  • fYear
    2007
  • fDate
    7-9 Nov. 2007
  • Firstpage
    21
  • Lastpage
    28
  • Abstract
    In this paper we develop a framework for fast and accurate multiprocessor system performance simulation. Our simulation model generator generates simulation modules with accurate time deltas for software processes based on the intermediate representations generated by a compiler. The simulation modules are simulated as concurrent tasks in multiprocessor system performance simulation environment in SystemC. We use aggregated waits to reduce overhead in the simulation kernel and triple the speed of the simulation. Our study shows that we can obtain overall system performance results with less than 6% error while simulating at 150times faster than using an Instruction Set Simulator. This opens up system design space explorations that were not possible before.
  • Keywords
    hardware description languages; instruction sets; multiprocessing systems; program compilers; program diagnostics; system-on-chip; SystemC environment; concurrent task; instruction set simulator; intermediate representations; multiprocessor system design performance simulation; software compiler; software process; Analytical models; Computational modeling; Computer architecture; Computer simulation; Kernel; Multiprocessing systems; Performance analysis; Software performance; Space exploration; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International
  • Conference_Location
    Irvine, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4244-1480-2
  • Type

    conf

  • DOI
    10.1109/HLDVT.2007.4392780
  • Filename
    4392780