• DocumentCode
    2270836
  • Title

    Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip

  • Author

    Cheung, Eric ; Hsieh, Harry ; Balarin, Felice

  • Author_Institution
    Univ. of California Riverside Riverside, Riverside
  • fYear
    2007
  • fDate
    7-9 Nov. 2007
  • Firstpage
    37
  • Lastpage
    44
  • Abstract
    Multiprocessor System-on-Chip (MPSoC) has emerged as the most promising architecture for future embedded system designs, and Kahn Process Networks (KPN) have been shown to be an excellent solution to model applications for MPSoC because it allows maximum freedom in implementation. However, the effects of buffer sizing for KPN applications on MPSoC are not well investigated. Sizes for the bounded FIFOs affect the parallelism in the implementations and the performance of the systems. To the best of our knowledge, buffer sizing for performance optimization in MPSOC has not been addressed before. We propose an off-line automatic buffer sizing algorithm based on the rate constraints and the dependency information gathered from the profiled results. The algorithm can be applied to rate-constraint application such as MPEG-2 decoder to determine the minimum buffer sizes that satisfies the constraints. Our study shows that our algorithm can automatically size the buffers such that the total buffer usage is reduced by orders of magnitude for a given rate constraint.
  • Keywords
    buffer storage; embedded systems; microprocessor chips; multiprocessing systems; parallel architectures; system-on-chip; MPEG-2 decoder; bounded FIFO sizing; embedded system design; multiprocessor system-on-chip architecture; offline automatic buffer sizing algorithm; performance optimization; rate-constrained Kahn process network application; Computational modeling; Computer networks; Decoding; Embedded system; Multiprocessing systems; Optimization; Parallel processing; Runtime; Streaming media; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International
  • Conference_Location
    Irvine, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4244-1480-2
  • Type

    conf

  • DOI
    10.1109/HLDVT.2007.4392782
  • Filename
    4392782