DocumentCode
2271062
Title
A Hardware-in-the-Loop Simulation Environment for Real-Time Systems Development and Architecture Evaluation
Author
Balashov, V.V. ; Bakhmurov, A.G. ; Chistolinov, M.V. ; Smeliansky, R.L. ; Volkanov, D.Yu. ; Youshchenko, N.V.
Author_Institution
Dept. of Comput. Math. & Cybern., Moscow State Univ., Moscow
fYear
2008
fDate
26-28 June 2008
Firstpage
80
Lastpage
86
Abstract
In this paper we present a technology for integration of distributed real-time embedded systems (RTES) based on hardware-in-the loop simulation. The environment to support this technology is described. This environment also enables simulation-based evaluation of RTES architecture on early stages of RTES development.
Keywords
embedded systems; performance evaluation; distributed real-time embedded systems; hardware-in-the-loop simulation environment; real-time systems development and architecture evaluation; Computational modeling; Computer architecture; Computer simulation; Cybernetics; Hardware; Mathematics; Real time systems; Scheduling; Software debugging; Software tools; architecture evaluation; hardware-in-the-loop simulation; real-time embedded systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependability of Computer Systems, 2008. DepCos-RELCOMEX '08. Third International Conference on
Conference_Location
Szklarska Poreba
Print_ISBN
978-0-7695-3179-3
Type
conf
DOI
10.1109/DepCoS-RELCOMEX.2008.11
Filename
4573043
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