A tool for automatic synthesis of fuzzy controllers

We present a two step synthesis approach to the design of VLSI fuzzy controllers. First, we derive a VHDL description of the ASIC from the problem specifications, the hardware constraints and the performance requirements. Then, we map the VHDL description to gate level description with a standard logic synthesis tool. The process is repeated until the resulting design is tuned to the global requirements of the control device in terms of performance and cost