Title :
Transactors for parallel hardware and software co-design
Author_Institution :
Comput. Sci. Div., Univ. of California at Berkeley, Berkeley, CA
Abstract :
The use of higher-level design specifications is required for large scale embedded systems, yet these must admit efficient hardware and software implementations. The transactor model separates local computation from global communication, and avoids overspecifying the execution of computations within each unit. The use of guarded atomic commands provides a clean model for concurrent activities that share state within each unit, and supports computations on non-deterministic input streams.
Keywords :
embedded systems; hardware-software codesign; logic design; parallel processing; concurrent activity; guarded atomic commands; higher-level design specifications; large scale embedded systems; parallel hardware and software co-design; transactor model; Circuit synthesis; Clocks; Computational modeling; Computer science; Design methodology; Embedded system; Hardware; Information processing; Network synthesis; Software design;
Conference_Titel :
High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International
Conference_Location :
Irvine, CA
Print_ISBN :
978-1-4244-1480-2
DOI :
10.1109/HLDVT.2007.4392802
