An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Author

Lin, Yi-Wei ; Tsai, Ming-Chien ; Yang, Hao-I ; Lin, Geng-Cing ; Wang, Shao-Cheng ; Chuang, Ching-Te ; Jou, Shyh-Jye ; Hwang, Wei ; Lien, Nan-Chun ; Lee, Kuen-Di ; Shih, Wei-Chiang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

4

Abstract

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V_read) and cell Inverter Trip voltage (V_trip) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V_read and V_trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.

Keywords

CMOS memory circuits; Monte Carlo methods; SRAM chips; circuit layout; circuit simulation; readout electronics; statistical analysis; voltage measurement; voltage-controlled oscillators; CMOS 6T SRAM array; Monte Carlo simulation; SRAM cell array environment; UMC 1P10M standard performance CMOS technology; all-digital read stability; cell inverter trip voltage measurement; cell read disturb voltage measurement; counter based digital read-out; data extraction; memory size 512 KByte; post-layout simulation; resistor based voltage divider; size 55 nm; statistical analysis; voltage 10 mV; voltage 640 mV; voltage controlled oscillator; write margin characterization scheme; Arrays; Inverters; Microprocessors; Random access memory; Voltage measurement; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

PENDING

Print_ISBN

978-1-4577-2080-2

Type

conf

DOI

10.1109/VLSI-DAT.2012.6212589

Filename

6212589