Title :
A slew rate self-adjusting 2×VDD output buffer With PVT compensation
Author :
Chen, Chih-Lin ; Tseng, Hsin-Yuan ; Kuo, Ron-Chi ; Wang, Chua-Chin
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 38% and the maximum data rate with compensation is 345 MHz.
Keywords :
CMOS integrated circuits; buffer circuits; compensation; integrated circuit design; CMOS process; NMOS; PMOS; PVT compensation; VDD output buffer; compensation technique; data rate; frequency 345 MHz; output current; process-voltage-temperature detection; size 90 nm; slew rate; threshold voltage; CMOS process; Digital circuits; Generators; MOS devices; Temperature sensors; Threshold voltage; I/O buffer; PVT variation; floating N-well circuit; gate-oxide reliability; mixed-voltage tolerant; threshold voltage detection;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2080-2
DOI :
10.1109/VLSI-DAT.2012.6212590
