Title :
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS
Author :
Danjo, Takumi ; Yoshioka, Masato ; Isogai, Masayuki ; Hoshino, Masanori ; Tsukamoto, Sanroku
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator operates twice each cycle, during coarse and fine decision, for a conversion based on digitally controlled threshold levels. The threshold levels at these decisions are different, so these are adjusted in foreground calibration. The die area is 0.04mm2 including on-chip digitally threshold control circuit, and power consumption is 9.9mW. SNDR is 32.8 dB is achieved at 1GS/s.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); interpolation; resistors; CMOS; SNDR; coarse decision; die area; digitally controlled threshold levels; fine decision; foreground calibration; interpolated subranging ADC; interpolating technique; noise figure 32.8 dB; on-chip digitally threshold control circuit; power 9.9 mW; power consumption; redundant comparators; reference resistor ladder; size 65 nm; word length 6 bit; CMOS integrated circuits; Calibration; Digital control; Interpolation; MOS devices; Power demand;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2080-2
DOI :
10.1109/VLSI-DAT.2012.6212591
