A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

Author

Chen, Yi-Hsun ; Yang, Chi-Heng ; Chang, Hsie-Chia

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.

Keywords

BCH codes; CMOS integrated circuits; NOR circuits; decoding; error correction codes; flash memories; logic gates; reliability; CMOS technology; DEC BCH decoder; NOR flash memories; checking equation; composite field arithmetic; decoding mechanism; double error correcting codes; fully-parallel architecture; logic gates; size 90 nm; Ash; Computer architecture; Decoding; Hardware; Iterative decoding; Polynomials; BCH codes; Composite field; Double-Error-Correcting; NOR flash memories; Step-by-step decoding algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

PENDING

Print_ISBN

978-1-4577-2080-2

Type

conf

DOI

10.1109/VLSI-DAT.2012.6212602

Filename

6212602